Intel AI Get-to Market Customer Success and Solutions 60489932ec sycl: Q5_K reorder MMVQ/dequant + Q8_0 reorder MMVQ path (#22152) ...

* sycl: Q5_K reorder MMVQ/dequant + Q8_0 reorder MMVQ path

Signed-off-by: Chun Tao <chun.tao@intel.com>

* Remove duplicate definitions

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Signed-off-by: Chun Tao <chun.tao@intel.com>
Co-authored-by: Chun Tao <chun.tao@intel.com>
Co-authored-by: Todd Malsbary <todd.malsbary@intel.com>

2026-05-09 08:48:07 +03:00

..

cmake

ggml: backend-agnostic tensor parallelism (experimental) (#19378)

2026-04-09 16:42:19 +02:00

include

CUDA: lower-case PCI bus id, standardize for ggml (#22820)

2026-05-08 10:09:38 +02:00

src

sycl: Q5_K reorder MMVQ/dequant + Q8_0 reorder MMVQ path (#22152)

2026-05-09 08:48:07 +03:00

.gitignore

vulkan : cmake integration (#8119)

2024-07-13 18:12:39 +02:00

CMakeLists.txt

ggml : bump version to 0.11.0 (ggml/1478)

2026-05-05 13:15:59 +03:00